Tolera (TEC2012-31292)

PVT-variations and radiation tolerance in nanometric technologies
(Tolerancia a variaciones PVT y radiación en tecnologías nanométricas)


CMOS integrated circuits fabricated with nanoscale technologies are subject to numerous uncertainties
related with second-order effects that were previously negligible but now limit the final performance of
the circuit and the manufacturing yield. Such is the case of process variations, or variations in the
environmental operating conditions (voltage drops, hot spots, failure due to radiation). In this project we
propose circuit level techniques aimed to achieve robust designs able to tolerate PVT variations and
radiation. Specifically we propose two main objectives:
To design, simulate and manufacture PVT variations sensors that can be integrated into a
variations monitoring network on-chip. The proposal includes critical path sensors (with a double
objective, measuring both process and aging variations), static power sensors and VDD
sensors. All these sensors have to be small, easily integrated in CMOS, low power and oriented
towards the constraints imposed by PVT variations monitoring. The sensors will be integrated into
a tester circuit of medium complexity.
To study and provide mechanisms for radiation-tolerant digital circuits by designing and
implementing a basic standard cell library radiation hardened. Hardening techniques will be
implemented at the physical (layout) and digital level and applied to a reduced set of basic logic
gates and flip-flops that must be big enough to satisfy the requirements of the synthesis tools. We
will perform an in-depth study of the tradeóff etween area, performance and the degree of
radiation toleration.
Finally, we propose the design of two sensors, for aging (through critical path) and temperature,
employing the developed radiation tolerance techniques. These sensors can be integrated into future
applications for high radiation environments, where remote monitoring plays a key role.



Journal Papers and Book Chapters

  1. A performance study of CUDA UVM vs. manual optimizations in a real-world setup: Application to a Monte Carlo wave-particle event-based interaction modeJose M. Nadal-Serrano and Marisa Lopez-Vallejo. IEEE Transactions on Parallel and Distributed Systems,  Nadal-Serrano, J. M., & Lopez-Vallejo, M. (2016).  June 2016, vol. 27, no 6, p. 1579-1588. Impact Factor 2016 4.181 (Q1).
  2. Efficient Mitigation of SET Induced Harmonic Errors in Ring Oscillators. A gustin, J., Lopez-Vallejo, M. L., Soriano, C. G., Cholbi, P., Massengill, L. W., & Chen, Y. P. (2015).Nuclear Science, IEEE Transactions on, vol. 62, no 6, p. 3049-3056. Dec. 2015. Impact Factor 2015 1.198.
  3. An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-CycleAgustin, J., & Lopez-Vallejo, M. (2015). IEEE Transactions on Circuits and Systems I: Regular Papers, I, vol. 62, no 10, p. 2485-2494. Oct. 2015. Impact Factor (2015): 2,393.
  4. A survey on theoretical and practical aspects of imaging aids for artificial vision in professional environmentsNadal-Serrano, J.M.; Lopez-Vallejo, M. Sensors Journal, IEEE , vol.15, no.5, pp.2719-2731, May 2015, Impact Factor 20151.889
  5. Design and Characterization of a Built-In CMOS TID Smart Sensor, Agustin, J.; Gil, C.; Lopez-Vallejo, M.; Ituero, P., Nuclear Science, IEEE Transactions on. April 2015vol.62, no.2, pp. 443-450.  Impact Factor 2015 1.198.
  6. Real-time low-complexity automatic modulation classifier for pulsed radar signals,Iglesias, V.; Grajal, J.; Royer, P.; Sanchez, M.A.; Lopez-Vallejo, M.; Yeste-Ojeda, O.A., Aerospace and Electronic Systems, IEEE Transactions on , vol.51, no.1, pp.108,126, January 2015. 
  7. Building Memristor Applications: From Device Model to Circuit Design. Fernando García, Marisa López-Vallejo, Pablo Ituero. IEEE Transactions on Nanotechnology. 2014. vol.13, no.6, pp.1154,1162, Nov. 2014. Impact Factor 2013: 1,619.
  8. Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies. P. Royer and M. Lopez-Vallejo. Nanotechnology, IEEE Transactions on , vol.13, no.6, pp.1226,1233, Nov. 2014.  Impact Factor 2013: 1,619
  9. A Self-Timed Multipurpose Delay Sensor for FPGAs. Carlos Gómez-Osuna, Pablo Ituero, Marisa López-Vallejo. Sensors n. 14(1), 2014 pp 129-143. Impact Factor 2014: 2.245
  10. System Design Framework and Methodology for Xilinx Virtex FPGA Configuration Scrubbers. Herrera-Alzu, I.; Lopez-Vallejo, M. Nuclear Science, IEEE Transactions on , vol.61, no.1, pp.619,629, Feb. 2014. Impact Factor 20141.283 (Q1)
  11. On-Chip Thermal Monitoring. Pablo Ituero, Marisa López-Vallejo. LAMBERT Academic Publishing. 2013. 188 pages. ISBN:978-3-659-51126-4.
  12. A 0.0016mm2 0.64nJ Leakage Based CMOS Temperature Sensor. Pablo Ituero, Marisa López-Vallejo, Carlos López-Barrio. Sensors 2013, no. 9, pp 12648-12662.  Impact Factor 2013: 2,048
  13. Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers, Ignacio Herrera-Alzu and Marisa López-Vallejo. IEEE Transactions on Nuclear Science (TNS), vol.60, no.1, pp.376,385, Feb. 2013. Impact Factor 2013 1.455 (Q1)
  14. Ratio-Based Temperature Sensing Technique Hardened Against Nanometer Process Variations. Pablo Ituero, Marisa López-Vallejo. IEEE Sensors Journal. vol. 13, issue 2, Fer. 2013, pp 442-443. Impact Factor 20131,852 
  15. Floating-Point Exponentiation Units for Reconfigurable Computing,  Florent De Dinechin  Pedro Echeverria  Marisa Lopez-VallejoBogdan Pasca, ACM Transactions on Recon.gurable Technology and Systems,  ACM Trans. Reconfigurable Technol. Syst. 6, 1, Article 4 (May 2013).

Conference Papers

  1. A Thermal Adaptive Scheme for Reliable Write Operation on RRAM Based Architecture. Fernando García-Redondo, Marisa Lopez-Vallejo and Pablo Ituero 33rd IEEE International Conference on Computer Design (ICCD). New York, Oct. 2015.
  2. A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs, Herrera-Alzu, I.; Lopez-Vallejo, M.; Gil Soriano, C., in Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on , vol., no., pp.72-75, 12-14 Oct. 2015.
  3. Efficient Mitigation of SET Induced Harmonic Errors in Ring Oscillators, J. Agustin, M. Lopez-Vallejo, L. W. Massengill, 2015 IEEE Nuclear \& Space Radiation Effects Conference (NSREC 2015), Boston, USA, July 2015.
  4. Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm, Royer, P.; Garcia-Redondo, F.; Lopez-Vallejo, M., in Nanoscale Architectures (NANOARCH), 2015 IEEE/ACM International Symposium on, pp.112-117, 8-10 July 2015.
  5. A built-in CMOS Total Ionization Dose smart sensorAgustin, J.; Soriano, C.G.; Lopez Vallejo, M.; Ituero, P., SENSORS, 2014 IEEE , vol., no., pp.70,73, 2-5 Nov. 2014.
  6. A Critical-Path Monitor for DVFS Systems without Datapath Replication. Hernán Cerqueira, Pablo Ituero and Marisa López-Vallejo. Conference on Design of Circuits and Integrated Systems  2014 (DCIS 2014).
  7. Implementation Tradeoffs of Triangle Traversal Algorithms for Graphics Processing. Pablo Royer, Pablo Ituero, Marisa López-Vallejo and Carlos A. López Barrio. Conference on Design of Circuits and Integrated Systems  2014 (DCIS 2014).
  8. Four-injector variability modeling of FinFET predictive technology models, Royer, P.; Lopez-Vallejo, M.; Garcia Redondo, F.; Lopez Barrio, C.A., 2014 5th European Workshop on CMOS Variability (VARI), vol., no., pp.1,6, Sept. 29 2014-Oct. 1 2014.
  9. A tool for the automatic analysis of single events effects on electronic circuits, Garcia-Redondo, F.; Lopez-Vallejo, M.; Royer, P.; Agustin, J., CMOS Variability (VARI), 2014 5th European Workshop on , vol., no., pp.1,6, Sept. 29 2014-Oct. 1 2014
  10. Real-time radar pulse parameter extractorIglesias, V.; Grajal, J.; Yeste-Ojeda, O.; Garrido, M.; Sanchez, M.A.; Lopez-Vallejo, M.,  Radar Conference, 2014 IEEE , vol., no., pp.0371,0375, 19-23 May 2014
  11. Circuit-level modeling of FinFet sub-threshold slope and DIBL mismatch beyond 22nm. Pablo Royer, Binjie Cheng, Asen Asenov, & Marisa López-Vallejo. 18th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2013). Glasgow, Scotland. September 2013.
  12. A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node. Pablo Royer, & Marisa López-Vallejo. 23rd ACM international conference on Great lakes symposium on VLSI (GLSVLSI 2013). Paris, France. May 2013.
  13. A Critical-Path Monitor for DVFS Systems without Datapath Replication. Hernán Aparicio, Pablo Ituero and Marisa López-Vallejo. Conference on Design of Circuits and Integrated Systems 2014 (DCIS 2014) Madrid (Spain) 26-28 November 2014. 
  14. A Low-Area Reference-Free Power Supply Sensor. Carlos Benito, Pablo Ituero and Marisa López-Vallejo. 16th EUROMICRO Conference on Digital System Design (DSD2013). Santander, Spain, September 4-6 2013.
  15. Improvement of Radar Capabilities by Reconfigurable Digital Signal Processing. Fernando García, Víctor Iglesias, Miguel A. Sánchez, Jesús Grajal, Marisa López-Vallejo, Carlos López-Barrio. Conference on Design of Circuits and Integrated Systems  2013 (DCIS 2013) San Sebastián (Spain).