Ruzica Jevtic‎ > ‎


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1. R. Jevtic and C. Carreras, "Power Measurement Methodology for FPGA devices", IEEE Trans. on Instrumentation and Measurement, to appear, 2010, Impact factor: 0.978.
2.  B. Jovanovic, R. Jevtic and C. Carreras, "Triple-bit method for power estimation of nonlinear digital circuits in FPGAs", Electronics Letters, vol. 46, num. 13, 2010. Impact factor: 1.14
3.  R. Jevtic and C. Carreras, "Power Estimation of Embedded Multipliers in FPGAs", IEEE Trans. on VLSI Systems, vol. 18, issue 5, pp. 835-839, May 2010, Impact factor: 1.373
4. R. Jevtic, C. Carreras and G. Caffarena, "Fast and Accurate Power Estimation of FPGA DSP Components Based on High-level Switching Activity Models", International Journal of Electronics, vol. 95, no. 7, pp. 653-668, July 2008, Impact factor: 0.567
1. R. Jevtic, C. Carreras and V. Pejovic, "Floorplan-based FPGA Interconnect Power Estimation in DSP circuits", SLIP'09, pp. 53-60, July, 2009.
2. R. Jevtic, C. Carreras and D. Helms, "A Comparison of Approaches for High-level Power Estimation of LUT-based DSP Components", ReConFig'08, pp. 361-366, December 2008.
3. R. Jevtic and C. Carreras, "Analytical High-level Power Model for LUT-based Components", PATMOS'08, LNCS, vol. 5349, pp. 369-378, Sept. 2008.
4. R. Jevtic and C. Carreras, G. Caffarena, "Switching Activity Models for Power Estimation in FPGA Multipliers", Int. Workshop on Applied Reconfigurable Computing, LNCS, vol. 4419, pp. 201-213, March 2007.
5. R. Jevtic, C. Carreras  and G. Caffarena, "High-level Switching Activity Models for Multipliers in FPGAs", ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, pp. 224-225, February 2007.