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NEUROWARE (PGC2018-097339)

Efficient and Robust Hardware for Brain-Inspired Computing (Neuroware)


NEUROWARE deals with one of the topics with most intensive activity for these and coming years: big data processing, and in particular
the area of efficient brain-inspired computing. Many applications require deep learning algorithms to be computed near to the source of
information, what imposes strict restrictions in terms of memory, computational costs and energy consumption along with adaptability to
the source environment. However, there is a growing gap between the needs of algorithms designed by data scientist and the capabilities
of the hardware available to accommodate them. These efficiency and energy gaps are not bridged by the technology reduction imposed
by Moores Law, there is a need for novel circuital and architectural paradigms.

In NEUROWARE we propose hardware architectures for brain-inspired computing that contribute to increase the efficiency of current
solutions to provide better performance and reduced energy consumption. The challenge is to implement reliable intelligence in edge
devices and platforms in a way that is efficient in terms of performance and power.

The general objectives of this project address some of these issues from the device, circuit and architectural levels. Neuroware plans to
explore the architectural limits of circuits implementing the basic processing element in deep neural network (DNN), the artificial neuron.
First it proposes digital implementations at circuit and architectural level targeting novel designs for DNN. Furthermore, since reliability is a
key issue in current nanometer technologies, it will also be studied the adaptability of DNN hardware to process, temperature, VDD,
radiation and aging variations.

A second objective of NEUROWARE is the exploration of circuits and architectures for the robust design of memristive-based braininspired
computing. There is a clear potential of ReRAM for DNN implementations, because it provides efficient implementation of
interconnections and computation in memory for brain-inspired circuits. This results in a reduction in data management and a significant
improvement in performance and energy savings. However, the immaturity of ReRAM technology makes designers face serious issues
like device non-uniformity, conductance level instability, sneak path currents, and wire resistance. This directly affects the reliability of the
implementation and has serious impact on the array size and system performance.

A last goal of NEUROWARE is the design of configurable hardware for the implementation of DNNs. This configurability will be studied
both for the design of digital artificial neurons and memristive architectures. Finally, the project proposes the combination of both digital
and analog memristor-based circuitries to conform efficient mixed-signal architectures.



Conference papers
  • “Temperature-aware writing architecture for multilevel memristive cells”, A. de Gracia and M. Lopez-Vallejo. 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). July 2019