MARCE Research Project
MARCE: Methods and architectures to reduce energy consumption (TIC2003-07036)
The current trend on the design of high-complexity applications
running on embedded systems requires the definition of hardware and
software architectures that can execute such applications efficiently
with new design constraints (low-power consumption). Additionally,
these optimizations have to be integrated in hw/sw design methodologies
to accelerate the complex embedded systems' design flow.
The main objectives of this project are the definition of design
methodologies, architectural modifications and software optimizations
to reduce power consumption and increase performance on general purpose
applications running on embedded systems.
Power minimization will begin with the definition of accurate
analytical power models, easily extensible, to validate future energy
saving techniques. Also, hardware modifications (computer architecture)
and software optimizations (compiler optimizations) will be provided.
These will also be implemented on real platforms (FPGAs and ALPHA
processors) and will simulate interesting applications.
The improvement of performance on embedded systems will be performed
by using static compilation techniques over multi-thread architectures
with tightly coupled functional units. These static compilation
techniques will be based on the definition of analytical function
models for the most interesting modules (memory hierarchy) that will
let us to apply compilation techniques to reduce the delay by cache
optimizations (loop unrolling, tiling, etc).
- From December 2003 to November 2006.
- Funded by the Spanish Ministry of Science and Education.
- "Reducing the Energy Consumption of the Register File for In-Order
Architectures" José L. Ayala, Marisa López-Vallejo, Alex Veidenbaum,
Carlos A. López. To be published in International Journal of Embedded Systems , February 2006.
- Integrating Functional and Power Simulation in Embedded Systems Design José L. Ayala, Marisa López-Vallejo. Journal of Embedded Computing, Vol. 1, No. 3, September 2004
- Power-Aware Compilation for Register File Energy Reduction José L. Ayala, Alexander Veidenbaum, Marisa López-Vallejo. International Journal of Parallel Programming (Kluwer Academic Publishers), Vol. 31, No. 6, pp. 449-465, December 2003.
- A Unified Framework for Power-Aware Design of Embedded Systems José L. Ayala, Marisa López-Vallejo. Lecture Notes on Computer Science (Springer Verlag) , vol. 2799, 2003
- Analysis of the Thermal Impact of Source-Code Transformations in Embedded Processors José L. Ayala, Cándido Méndez, Marisa López-Vallejo. IEEE International Conference on Electronics, Circuits and Systems, Nice (France), December 2006.
- Implementation Trade-offs of the Jacobian Logarithm for Several Hardware Platforms. Pablo Ituero, Pedro Echeverría, Marisa López-Vallejo and Carlos López-Barrio. XXI Conference on Design of Circuits and Integrated Systems. Barcelona 22-24 November 2006.
- Target Independent Thermal Modeling for Embedded Processors Cándido Méndez, José L. Ayala, Marisa López-Vallejo. IEEE Symposium on Industrial Embedded Systems, Antibes (France), October 2006.
- Compiler-driven Leakage Energy Reduction in Banked Register Files David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo. IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, Montpellier (France), September 2006.
- New Schemes in Clustered VLIW Processors Applied to Turbo Decoding.P. Ituero, M. López-Vallejo. 17th IEEE International Conference on Application-Specific Systems, Architecture Processors, Steamboat Springs, Colorado, September 11-13, 2006
- A Banked Precomputation-Based CAM Architecture for Low-Power Storage-Demanding Applications Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. IEEE Mediterranean Electrotechnical Conference, Malaga (Spain), May 2006.
- A Low-Power Pipelined CAM for High-Performance IP Routing Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. IEEE International Caribbean Conference on Devices, Circuits and Systems, Playa del Carmen (Mexico), April 2006.
- Energy-Aware Compilation and Delay Impact Minimization for VLIW Embedded Systems José L. Ayala, David Atienza, Praveen Raghavan, Marisa López-Vallejo, Francky Catthoor. IEEE Workshop on Innovative Architectures, Hawaii, January 2006.
- Practical Implementation of Low-Power Content Addressable Memories
Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. Design of
Circuits and Integrated Systems Conference, Lisboa (Portugal), November
- Optimal Loop-Unrolling Mechanisms and Architectural Extensions for
an Energy-Efficient Design of Shared Register Files in MPSoCs
José L. Ayala, David Atienza, Marisa López-Vallejo, José M. Mendías,
Román Hermida, Carlos A. López. IEEE Workshop on Innovative
Architectures, Hawaii, January 2005.
- Power Characterization of RAMs. An Experimental Approach
F. Javier Rellán, José L. Ayala, Marisa López-Vallejo. Design of
Circuits and Integrated Systems Conference, Bordeaux (France), November
- Improving Register File Banking with a Power-Aware Unroller José L. Ayala, Marisa López-Vallejo. Workshop on Power-Aware Real-Time Computing ( in conjunction with ACM International Conference on Embedded Software ), Pisa (Italy), September 2004.
- A Compiler-assisted Banked Register File Architecture José L. Ayala, Marisa López-Vallejo, Alex Veidenbaum. IEEE Workshop on Application Specific Processors ( in conjunction with IEEE International Conference on Hardware/Software Codesign and System Synthesis ), Stockholm (Sweden), September 2004.
- Power Estimation and Power Optimization Policies for Processor-Based Systems
José L. Ayala, Marisa López-Vallejo. SIGDA Ph.D. Forum at Design
Automation Conference, San Diego (California, USA), June 2004. (also
the poster )
- Power-aware Register Renaming in High-Performance Processors using Compiler Support José L. Ayala, Marisa López-Vallejo, Alex Veidenbaum. IEEE Workshop on Innovative Architectures, Hawaii, January 2004.
- Energy-Efficient Register Renaming in High-Performance Processors José L. Ayala, Marisa López-Vallejo, Alex Veidenbaum. IEEE Workshop on Application Specific Processors ( in conjunction with IEEE International Symposium on Microarchitecture ), San Diego (California, USA), December 2003.