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Journal Papers
- Floating-Point Exponentiation Units for Reconfigurable Computing, Florent De Dinechin, Pedro Echeverria, Marisa Lopez-Vallejo, Bogdan Pasca. ACM Transactions on Reconfigurable Technology and Systems, 2012 Accepted.
- High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator, Pedro Echeverría, Marisa López-Vallejo. Journal of Signal Processing Systems, Springer New York, 2012 Issn: 1939-8018, Doi: 10.1007/s11265-012-0684-4, Impact Factor 2011: 0.672.
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs, Pedro Echeverría, Marisa López-Vallejo, Microprocessors and Microsystems, Volume 35, Issue 6, August 2011, Pages 535-546, ISSN 0141-9331, 10.1016/j.micpro.2011.04.004. Impact Factor 2010: 0.545. Power Considerations in Banked CAMs: A leakage Reduction Approach P. Echeverría, José L. Ayala and M. López-Vallejo. Hindawi Journal on VLSI Design, vol 8, Issue 2, January 2008.
Conference Papers- FPGA Acceleration of Monte Carlo-based Financial Simulation: Design Challenges and Lessons Learnt, Pedro Echeverría, Marisa López-Vallejo. Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, DATE 2011, Grenoble (France), March 2011.
- Exploring Performance-Power Trade-offs forLook-Up Tables in
SRAM-based FPGAs, Pedro Echeverría, Marisa López-Vallejo, Walter
Bolognesi, Carlos López-Barrio. IEEE
International Conference on Electronics, Circuits and Systems, ICECS
2009, Tunisia December 2009.
- Development of a standard single floating-point library and its encapsulation for reuse, Pedro Echeverría, Miguel Angel Sánchez, Marisa López-Vallejo, Carlos López Barrio. Design of Circuits and
Integrated Systems Conference, Zaragoza (Spain), November 2009.
- Inversion-based FPGA Random Number Generation using Quintic Hermite Interpolation, Pedro Echeverría, Marisa López-Vallejo, Carlos López-Barrio. Design of Circuits and
Integrated Systems Conference, Grenoble (France), November 2008.
- Designing Highly Parameterized Hardware using xHDL, Miguel Angel Sanchez, Pedro Echeverría, Francisco Mansilla and Marisa López-Vallejo. Forum on Specification & Design Languages, FDL'08. Sttugart (Germany) September 2008.
- Variance Reduction Techniques for Monte Carlo Simulations. A Parameterizable FPGA Approach. Pedro Echeverría, Marisa López-Vallejo and José María Pesquero. IEEE
International Conference on Electronics, Circuits and Systems, ICECS 2008, Malta. Sept. 2008.
- Experimental Methodology for Power Characterization of FPGAs Ignacio
Herrera-Alzu, Miguel-Angel Sánchez-Marcos, Marisa López-Vallejo and
Pedro Echeverría. IEEE
International Conference on Electronics, Circuits and Systems, ICECS
2008, Malta. Sept. 2008.
- An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithmetic P. Echeverría and M. López-Vallejo. 8th Conference on Real Numbers and Computers, Santiago de Compostela (Spain), July 2008.
- An FPGA run-time parameterisable Log-Normal Random Number Generator P. Echeverría, D. B. Thomas, M. López-Vallejo and W. Luk. International Workshop on Applied Reconfigurable Computing, London (United Kingdom), March 2008
- FPGA Gaussian Random Number Generator based on quintic Hermite interpolation inversion
Pedro Echeverría and Marisa López-Vallejo. IEEE International Midwest
Symposium on Circuits and Systems, Montreal (Canada), August 2007.
- Leakage Energy Reduction in Banked Content Addressable Memories.
Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. IEEE
International Conference on Electronics, Circuits and Systems, Nice
(France), December 2006.
- Implementation Trade-offs of the Jacobian Logarithm for Several
Hardware Platforms P. Ituero, P. Echeverría, M.
López-Vallejo and C. López-Barrio. 21st Conference on Design of Circuits and
Integrated Systems, Barcelona (Spain) 22-24 November 2006.
- A Banked Precomputation-Based CAM Architecture for Low-Power Storage-Demanding Applications
P. Echeverría, José L. Ayala and M. López-Vallejo. IEEE
Mediterranean Electrotechnical Conference, Malaga (Spain), May 2006.
- A Low-Power Pipelined CAM for High-Performance IP Routing
P. Echeverría, José L. Ayala and M. López-Vallejo. IEEE
International Caribbean Conference on Devices, Circuits and Systems,
Playa del Carmen (Mexico), April 2006.
- Practical Implementation of Low-Power Content Addressable Memories
P. Echeverría, J. L. Ayala and M. López-Vallejo. Design of Circuits and
Integrated Systems Conference, Lisboa (Portugal), November 2005.
Ph.D Thesis
Master Thesis
- Diseño, simulación y caracterización de memorias de acceso por contenido (Design, simulation and characterization of Content-Addressable Memories) P. Echeverría. Master of Science Thesis. Advised by J. L. Ayala and M. López-Vallejo. Department of Electronic Engineering. Universidad Politécnica de Madrid, Diciembre 2005.
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