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Publications

Conference Papers

On the Hardware Implementation of Triangle Traversal Algorithms for Graphics Processing. Pablo Royer, Pablo Ituero, Marisa López-Vallejo, & Carlos A. López Barrio. 25th Conference on Design of Circuits and Integrated Systems 2010 (DCIS 2010). Lanzarote, Spain. November 2010.

Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs. Pablo Royer, Miguel A. Sanchez, Marisa López-Vallejo, & Carlos A. López Barrio. 26th Conference on Design of Circuits and Integrated Systems 2011 (DCIS 2011). Albufeira, Portugal. November 2011.

A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node. Pablo Royer, & Marisa López-Vallejo. 23rd ACM international conference on Great lakes symposium on VLSI (GLSVLSI 2013). Paris, France. May 2013.

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer del Barrio, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, & Diederik Verkest. 50th Annual Design Automation Conference (DAC 2013). Austin, TX, USA. June 2013.

Circuit-level modeling of FinFet sub-threshold slope and DIBL mismatch beyond 22nm. Pablo Royer, Binjie Cheng, Asen Asenov, & Marisa López-Vallejo. 18th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2013). Glasgow, Scotland. September 2013.

Master Theses

FPGA Design and Implementation of Critical Stages of a Graphics Processing Unit. Pablo Royer. Proyecto Fin de Carrera. Advised by Pablo Ituero Herrero. Department of Electronic Engineering. Universidad Politécnica of Madrid, June 2010.

FPGA Design and Implementation of Basic Modules for an Automatic Modulation Classifier. Pablo Royer. Proyecto Fin de Máster. Advised by Marisa López-Vallejo. Department of Electronic Engineering. Universidad Politécnica of Madrid, July 2011.


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