Publications
Please note that all publications listed and/or posted
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PVT-Aware Design
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On-Chip Monitoring: A Light-Weight Interconnection Network Approach. Pablo Ituero, Marisa López-Vallejo, Miguel A. Sánchez Marcos, Carlos Gómez Osuna. 14th EUROMICRO Conference on Digital System Design. Architectures, Methods and Tools (DSD2011). Oulu, Finland, August 31 - September 2 2011.PVT Variations Monitoring in Nanometer CMOS ICs. Pablo Ituero, Marisa López-Vallejo. 2011 CMOS Emerging Technologies. Whistler, BC, Canada. 15-17 June 2011.System-on-Chip monitoring networks targeting nanometer technologies. Marisa López-Vallejo, Pablo Ituero. 2010 CMOS Emerging Technologies. Whistler, BC, Canada. 19-21 May 2010.
Thermal analysis and modeling of embedded processors. José L. Ayala, Cándido Méndez, Marisa López-Vallejo. Computers & Electrical Engineering
Volume 36, Issue 1, January 2010, Pages 142-154. Impact Factor 2009: 0.475
A Nanowatt Smart Thermal Sensor for Dynamic Temperature Management Pablo Ituero, José Luis Ayala, and Marisa López-Vallejo. IEEE Sensors Journal. Dec. 2008. Impact Factor 2006:
1,340
A Novel Small Low-Power Interface for On-Chip Thermal Sensors
Pablo Ituero, José L. Ayala and Marisa López-Vallejo. 23rd Conference on Design of Circuits and
Integrated Systems (DCIS'08). Grenoble, France 12-14 November 2008.
Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems.
Ayala, Jose L.; Apavatjrut, Anya; Atienza, David; Lopez-Vallejo,
Marisa. IEEE International Workshop on Innovative Architecture for
Future Generation Processors and Systems, 2007. IWIA 2007. 11-13 Jan.
2007
Page(s):81 - 87.
Leakage-based On-Chip Thermal Sensor for CMOS Technology
Pablo Ituero, José L. Ayala and Marisa López-Vallejo. IEEE
International Symposium on Circuits and Systems, New Orleans, May
27-30, 2007. |
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Analysis of the Thermal Impact of Source-Code Transformations in Embedded Processors
José L. Ayala, Cándido Méndez, Marisa López-Vallejo. IEEE International
Conference on Electronics, Circuits and Systems, Nice (France),
December 2006. |
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Target Independent Thermal Modeling for Embedded Processors
Cándido Méndez, José L. Ayala, Marisa López-Vallejo. IEEE Symposium on
Industrial Embedded Systems, Antibes (France), October 2006. |
High Performance Digital Design in Reconfigurable Architectures
Implementing FFT-based Digital Channelized Receivers on FPGA Platforms, M. A. Sánchez, M. Garrido, M. L. López Vallejo y J. Grajal, IEEE Trans. on Aeroespace and Electronic Systems.October 2008. Impact Factor 2008: 1,024.
Development of a standard single floating-point library and its encapsulation for reuse, Pedro Echeverría, Miguel Angel Sánchez, Marisa López-Vallejo, Carlos López Barrio. Design of Circuits and Integrated Systems Conference, Zaragoza (Spain), November 2009.
Inversion-based FPGA Random Number Generation using Quintic Hermite Interpolation, Pedro Echeverría, Marisa López-Vallejo, Carlos López-Barrio. Design of Circuits and Integrated Systems Conference, Grenoble (France), November 2008. Designing Highly Parameterized Hardware using xHDL, Miguel Angel Sanchez, Pedro Echeverría, Francisco Mansilla and Marisa López-Vallejo. Forum on Specification & Design Languages, FDL'08. Sttugart (Germany) September 2008.
Variance Reduction Techniques for Monte Carlo Simulations. A Parameterizable FPGA Approach. Pedro Echeverría, Marisa López-Vallejo, José María Pesquero. IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, Malta. Sept. 2008.
An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithmetic P. Echeverría and M. López-Vallejo. 8th Conference on Real Numbers and Computers, Santiago de Compostela (Spain), July 2008. An FPGA run-time parameterisable Log-Normal Random Number Generator P. Echeverría, D. B. Thomas, M. López-Vallejo and W. Luk. International Workshop on Applied Reconfigurable Computing, London (United Kingdom), March 2008 FPGA Gaussian Random Number Generator based on quintic Hermite interpolation inversion Pedro Echeverría and Marisa López-Vallejo. IEEE International Midwest Symposium on Circuits and Systems, Montreal (Canada), August 2007. Implementation Trade-offs of the Jacobian Logarithm for Several Hardware Platforms. Pablo Ituero, Pedro Echeverría, Marisa López-Vallejo and Carlos López-Barrio. XXI Conference on Design of Circuits and Integrated Systems. Barcelona 22-24 November 2006. Design of a Pipelined Hardware Architecture for Real-Time Neural Network Computations. J. L. Ayala, A. G. Lomeña, M. López-Vallejo, A. Fernández. IEEE Midwest Symposium on Circuits and Systems, Tulsa (Oklahoma, USA), August 2002 A Fast, Configurable Digital Neural Network ASIC for High-Speed Applications. J. L. Ayala, A. G. Lomeña, M. López-Vallejo, A. Fernández. Design of Circuits and Integrated Systems Conference, Oporto (Portugal), November 2001
Low Power Design
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Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs, Echeverria, P.; Lopez-Vallejo, M.; Bolognesi, W.; Lopez-Barrio, C.; , Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on , vol., no., pp.423-426, 13-16 Dec. 2009
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. José Luis Ayala, Marisa López-Vallejo, Carlos A. López Barrio and Alex Veidenvaum.
International Journal of Embedded Systems 2008 - Vol. 3, No.4 pp. 285 - 293.
Experimental Methodology for Power Characterization of FPGAs Ignacio
Herrera-Alzu, Miguel-Angel Sánchez-Marcos, Marisa López-Vallejo and
Pedro Echeverría. IEEE
International Conference on Electronics, Circuits and Systems, ICECS
2008, Malta. Sept. 2008.
Joint Hardware-Software Leakage
Minimization Approach For The Register File of VLIW Embedded Architectures. D. Atienza, , P. Raghavan, J. L. Ayala, G. De
Micheli, F. Catthoor, D. Verkerst, M. López-Vallejo. Integration, The VLSI Journal, vol 41, issue1, pp 38-48, Jan. 2008. Impact
Factor: 0,4
Power Considerations in Banked CAMs: A leakage Reduction Approach P. Echeverría and M. López-Vallejo. Hindawi Journal on VLSI Design, vol 8, Issue 2, January 2008.
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors, Raghavan, P.; Ayala, J.L.; Atienza, D.; Catthoor, F.; De Micheli, G.; Lopez-Vallejo, M., Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on , vol., no., pp.121-124, 27-30 May 2007.
Leakage Energy Reduction in Banked Content Addressable Memories.
Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. IEEE
International Conference on Electronics, Circuits and Systems, Nice
(France), December 2006. |
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Automated design space exploration of FPGA-based FFT architectures based on area and power estimation,
Sanchez, M.A.; Garrido, M.; Vallejo, M.L.; Lopez-Barrio, C.; IEEE
International Conference on Field Programmable Technology, 2006. FPT
2006. Dec. 2006
Page(s):127 - 134.
Energy-Aware Compilation and Hardware Design for VLIW Embedded Systems.
José L. Ayala, David Atienza, Praveen Raghavan, Marisa López-Vallejo,
Francky Catthoor, Diederik Verkest. International Journal of Embedded
Systems, vol. 3, issue 1-2, pp. 73-82, 2007. |
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Compiler-driven Leakage Energy Reduction in Banked Register Files
David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli,
Francky Catthoor, Diederik Verkest, Marisa López-Vallejo. IEEE
International Workshop on Power and Timing Modeling, Optimization and
Simulation, Montpellier (France), September 2006. |
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A Banked Precomputation-Based CAM Architecture for Low-Power Storage-Demanding Applications
Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. IEEE
Mediterranean Electrotechnical Conference, Malaga (Spain), May 2006. |
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A Low-Power Pipelined CAM for High-Performance IP Routing
Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. IEEE
International Caribbean Conference on Devices, Circuits and Systems,
Playa del Carmen (Mexico), April 2006. |
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Energy-Aware Compilation and Delay Impact Minimization for VLIW Embedded Systems
José L. Ayala, David Atienza, Praveen Raghavan, Marisa López-Vallejo,
Francky Catthoor. IEEE Workshop on Innovative Architectures, Hawaii,
January 2006. |
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Practical Implementation of Low-Power Content Addressable Memories
P. Echeverría, J. L. Ayala, M. López-Vallejo. Design of Circuits and
Integrated Systems Conference, Lisboa (Portugal), November 2005. |
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Optimal Loop-Unrolling Mechanisms and Architectural Extensions for
an Energy-Efficient Design of Shared Register Files in MPSoCs
J. L. Ayala, D. Atienza, M. López-Vallejo, J. M. Mendías, R. Hermida,
C. A. López. IEEE Workshop on Innovative Architectures, Hawaii, January
2005. |
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Reducing the Energy Consumption of the Register File for In-Order Architectures
J. L. Ayala, M. López-Vallejo, Alex Veidenbaum, Carlos A. López. To be
published in International Journal of Embedded Systems , February 2005.
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Integrating Functional and Power Simulation in Embedded Systems Design J. L. Ayala, M. López-Vallejo. To be published in Journal of Embedded Computing, Fall 2004.
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Power Characterization of RAMs. An Experimental Approach
F. Rellán, J. L. Ayala, M. López-Vallejo. Design of Circuits and
Integrated Systems Conference, Bordeaux (France), November 2004. |
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Improving Register File Banking with a Power-Aware Unroller J. L. Ayala, M. López-Vallejo. Workshop on Power-Aware Real-Time Computing (in conjunction with ACM International Conference on Embedded Software), Pisa (Italy), September 2004.
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A Compiler-assisted Banked Register File Architecture J. L. Ayala, M. López-Vallejo, A. Veidenbaum. Workshop on Application Specific
Processors (in conjunction with IEEE International Conference on Hardware/Software Codesign and System Synthesis), Stockholm (Sweden),
September 2004.
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Power Estimation and Power Optimization Policies for Processor-Based Systems. J. L. Ayala, M. López-Vallejo. SIGDA Ph.D. Forum at Design Automation Conference, San Diego (California, USA),
June 2004. (see also the poster)
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Power-aware Register Renaming in High-Performance Processors using Compiler Support. J. L. Ayala, M. López-Vallejo, A. Veidenbaum. IEEE Workshop on Innovative Architectures, Hawaii,
January 2004.
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Energy-Efficient Register Renaming in High-Performance Processors. J. L. Ayala, M. López-Vallejo, A. Veidenbaum. Workshop on Application Specific
Processors (in conjunction with IEEE International
Symposium on Microarchitecture), San Diego (California, USA),
December 2003.
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Power-Aware Compilation for Register File Energy Reduction.
J. L. Ayala, A. Veidenbaum, M. López-Vallejo. International Journal of
Parallel Programming (Kluwer Academic Publishers), Vol. 31, No. 6, pp.
449-465, December 2003. Impact Factor 2006: 0,289
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A Case Study on Power Dissipation in the Memory Hierarchy of Embedded Systems. J. L.
Ayala, M. López-Vallejo and C.A. López Barrio. Design of Circuits and Integrated Systems Conference, Ciudad Real
(Spain), November 2003
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A Unified Framework for Power-Aware Design of Embedded Systems. J. L.
Ayala, M. López-Vallejo. IEEE International Workshop on
Power and Timing Modeling, Optimization and Simulation, Torino
(Italy), September 2003. Also published as Lecture Notes on Computer Science, vol. 2799 (Springer Verlag) |
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Energy Aware Register File
Implementation through Instruction Predecode.. J. L.
Ayala, M. López-Vallejo, A. Veidenbaum, C. A. López. IEEE International Conference on
Application-Specific Systems, Architectures and Processors, The Hague
(Netherlands), June 2003
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Reducing Register File
Energy Consumption using Compiler Support.. J. L.
Ayala, A. Veidenbaum. Workshop on Application Specific
Processors (in conjunction with IEEE International
Symposium on Microarchitecture), Istanbul (Turkey),
November 2002. Best Student Paper Award |
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A Low-Power
Architecture for Maximum a Posteriori Decoding. M.L.
López-Vallejo, S. A. Mujtaba and I. Lee. IEEE
Asilomar Conference 2002, California, USA. November 2002.
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Data-Quantization
Policies for Power and Area Minimization of
Hardware Neural Networks. J. L. Ayala, M.
López-Vallejo. Design of Circuits and Integrated Systems
Conference, Santander (Spain), November 2002
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Block Processing Technique for
Low Power Turbo Decoder Design. I. Lee, M.L. López Vallejo y S. A.
Mujtaba. Vehicular Technology Conference 2002, Birmingham, Al, USA.
Mayo 2002
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Application Specific Architectures
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Further Specialization of Clustered VLIW Processors: A MAP
Decoder for Software Defined Radio Pablo Ituero, and Marisa
López-Vallejo, ETRI Journal, vol.30, no.1, Feb. 2008, pp.113-128. Impact Factor 2006:
1,159
Joint Source-Channel Decoding ASIP Architecture for Sensor
Networks Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa
López-Vallejo, Pedro M. Crespo, Vicente Atxa, and Jon Altuna. Lecture Notes on Computer Science, vol. 4523, pp.
221–231, 2007. Springer-Verlag Berlin Heidelberg 2007
New Schemes in Clustered VLIW
Processors Applied to Turbo Decoding.P. Ituero, M. López-Vallejo.
17th IEEE International Conference on Application-Specific Systems,
Architecture Processors, Steamboat Springs, Colorado, September 11-13, 2006 |
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A Configurable Application
Specific Processor for Turbo Decoding. P. Ituero, M. Lopez-Vallejo,
S.A. Mujtaba. Conference Record of the Thirty-Ninth Asilomar Conference on
Signals, Systems and Computers. October 28 - November 1, 2005 Page(s):1356 -
1360 |
Embedded Systems Design Automation
| On the Hardware-Software Partitioning Problem: System Modeling and
Partitioning Techniques.
M. López-Vallejo and J. C. López.
ACM Trans. on Design Automation of Electronic Systems, July 2003, Vol. 8 Issue 3. Impact Factor 2006: 0,519.
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| State Space Compression in History Driven Quasi-Static
Scheduling A. G. Lomeña Moreno, M. L. López Vallejo, Y. Watanabe and A. Kondratyev. in Embedded Software for SOC. Kluwer Academic
Publishers (currently in press, to be published on June 2003)
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| An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. A. G. Lomeña Moreno, M. L. López Vallejo, Y. Watanabe
and A. Kondratyev. Design Automation and Test in Europe Conference, Munich, Germany, 3-7 March 2003
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| Aplicacion
de metodologias de co-diseno hw/sw de sistemas empotrados para el
diseno e implementacion de un control de accesos distribuido.
J. L. Ayala, A. G. Lomena, M. Lopez-Vallejo.
Telecommunication Electronics and Control, Santiago de Cuba (Cuba), July 2002 (in Spanish).
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| Hardware-Software Co-design
of a Cryptographic Application. D. Matilla, M. López-Vallejo, A.
Royo. Design of
Circuits and Integrated Systems Conference, Oporto
(Portugal), November 2001, pp 100-105.
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| Applying Data Mining Techniques to Tune System
Scheduling A. G. Lomeña Moreno, M. L. López Vallejo and A.
García Quintas. XVI Design of Circuits and Integrated Systems Conference, Oporto, Portugal, November 20-23, 2001
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| Multi-way Clustering
Techniques for System Level Partitioning. M. López-Vallejo,
and J.C. López. 14th IEEE ASIC/SOC Conference, Washington DC, September 2001,
pp. 242-247
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| Constraint-driven System Level
Partitioning. M. López-Vallejo, J. Grajal
and J.C. López. IEEE DATE Conference, Paris, March 2000,
pp. 411-416.
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| A Reed-Solomon Encoder/Decoder ASIC for Application
in ATM Networks. A. G. Lomeña Moreno, J. C. López López
and A. Royo Oreja. User Forum Design Automation and Test in Europe Conference, Paris, France, March 27-30, 2000 (Abstract), (Poster)
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| Hardware-Software Partitioning at the Knowledge
Level. M.L. López Vallejo, J.C. López and C.A.
Iglesias. Journal of Applied Intelligence, March 1999,
pp. 173-184.
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Education on Electronics Providing
Self-learning to Students of Highly Attended Electronics Courses
through the Remote Access to a Microelectronics Laboratory.
Marisa López-Vallejo, Ángel Fernández, Pablo Ituero y Gabriel
Caffarena, IEEE EAEEIE Annual Conference. Valencia 22-24 June 2009
Acceso Remoto al Laboratorio de Diseño Microelectrónico como Complemento a las Asignaturas Teóricas Relacionadas.
Marisa López-Vallejo, Ángel Fernández, Pablo Ituero y Gabriel
Caffarena. II Jornadas Internacionales U.P.M sobre Innovación
Educativa y Convergencia Europea (INECE'08). Madrid, Spain 9-11
December 2008.
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