Publications

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PVT-Aware Design

  1. A Critical-Path Monitor for DVFS Systems without Datapath Replication. Hernán Aparicio, Pablo Ituero and Marisa López-Vallejo. Conference on Design of Circuits and Integrated Systems 2014 (DCIS 2014) Madrid (Spain) 26-28 November 2014. 
  2. Implementation Tradeoffs of Triangle Traversal Algorithms for Graphics Processing. Pablo Royer, Pablo Ituero, Marisa López-Vallejo and Carlos A. López Barrio. Conference on Design of Circuits and Integrated Systems 2014 (DCIS 2014) Madrid (Spain) 26-28 November 2014. 
  3. A Built-in CMOS Total Ionization Dose Smart Sensor. Javier Agustín, Carlos Gil Soriano, Marisa López-Vallejo and Pablo Ituero. IEEE Sensors Conference 2014. Valencia, Spain. November 2-5 2014.
  4. On-Chip Thermal Monitoring. Pablo Ituero, Marisa López-Vallejo. LAMBERT Academic Publishing. 2013. 188 pages. ISBN: 978-3-659-51126-4.
  5. A Self-Timed Multipurpose Delay Sensor for FPGAs. Carlos Gómez-Osuna, Pablo Ituero, Marisa López-Vallejo. Sensors n. 14(1), Dic. 2013, pp 129-143. Impact Factor 2013: 2,048
  6. A 0.0016mm2 0.64nJ Leakage Based CMOS Temperature Sensor. Pablo Ituero, Marisa López-Vallejo, Carlos López-Barrio. Sensors 2013, no. 9, pp 12648-12662. Impact Factor 2013: 2,048
  7. Ratio-Based Temperature Sensing Technique Hardened Against Nanometer Process Variations. Pablo Ituero, Marisa López-Vallejo. IEEE Sensors Journal. vol. 13, issue 2, Fer. 2013, pp 442-443. Impact Factor 2013: 1,852
  8. A Low-Area Reference-Free Power Supply Sensor. Carlos Benito, Pablo Ituero and Marisa López-Vallejo. 16th EUROMICRO Conference on Digital System Design (DSD2013). Santander, Spain, September 4-6 2013.
  9. A Monitoring Infrastructure for FPGA Self-Awareness and Dynamic Adaptation. Carlos Gómez Osuna, Miguel Ángel Sánchez Marcos, Pablo Ituero and Marisa López-Vallejo. IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012). Seville (Spain) 09-12 December 2012.
  10. Temperature Sensor Placement Including Routing Overhead and Sampling Inaccuracies. Pablo Ituero, Fernando García, and Marisa López-Vallejo.IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2012 (SMACD2012) Seville, Spain. 19 - 21 September 2012.
  11. A Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration. Pablo Ituero, Marisa López-Vallejo, Miguel A. Sánchez Marcos, Carlos Gómez Osuna. IEEE Sensors Journal. Volume: 12 , Issue: 6, June 2012.
  12. On-Chip Monitoring: A Light-Weight Interconnection Network Approach. Pablo Ituero, Marisa López-Vallejo, Miguel A. Sánchez Marcos, Carlos Gómez Osuna. 14th EUROMICRO Conference on Digital System Design. Architectures, Methods and Tools (DSD2011). Oulu, Finland, August 31 - September 2 2011.
  13. PVT Variations Monitoring in Nanometer CMOS ICs. Pablo Ituero, Marisa López-Vallejo. 2011 CMOS Emerging Technologies. Whistler, BC, Canada. 15-17 June 2011.
  14. System-on-Chip monitoring networks targeting nanometer technologies. Marisa López-Vallejo, Pablo Ituero. 2010 CMOS Emerging Technologies. Whistler, BC, Canada. 19-21 May 2010.
  15. Thermal analysis and modeling of embedded processors. José L. Ayala, Cándido Méndez, Marisa López-Vallejo. Computers & Electrical Engineering
  16. Volume 36, Issue 1, January 2010, Pages 142-154. Impact Factor 2010: 0.484
  17. A Nanowatt Smart Thermal Sensor for Dynamic Temperature Management Pablo Ituero, José Luis Ayala, and Marisa López-Vallejo. IEEE Sensors Journal. Dec. 2008, pp.2036-2046. Impact Factor 2008: 1,818 
  18. A Novel Small Low-Power Interface for On-Chip Thermal Sensors Pablo Ituero, José L. Ayala and Marisa López-Vallejo. 23rd Conference on Design of Circuits and Integrated Systems (DCIS'08). Grenoble, France 12-14 November 2008.
  19. Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems. Ayala, Jose L.; Apavatjrut, Anya; Atienza, David; Lopez-Vallejo, Marisa. IEEE International Workshop on Innovative Architecture for Future Generation Processors and Systems, 2007. IWIA 2007. 11-13 Jan. 2007 Page(s):81 - 87.
  20. Leakage-based On-Chip Thermal Sensor for CMOS Technology Pablo Ituero, José L. Ayala and Marisa López-Vallejo. IEEE International Symposium on Circuits and Systems, New Orleans, May 27-30, 2007.
  21. Analysis of the Thermal Impact of Source-Code Transformations in Embedded Processors José L. Ayala, Cándido Méndez, Marisa López-Vallejo. IEEE International Conference on Electronics, Circuits and Systems, Nice (France), December 2006.
  22. Target Independent Thermal Modeling for Embedded Processors Cándido Méndez, José L. Ayala, Marisa López-Vallejo. IEEE Symposium on Industrial Embedded Systems, Antibes (France), October 2006.

Emerging Technologies

  1. Building Memristor Applications: From Device Model to Circuit Design. Fernando García, Marisa López-Vallejo, Pablo Ituero. IEEE Transactions on Nanotechnology. 2014. Accepted for publication. Impact Factor 2013: 1,619
  2. Circuit-level modeling of FinFet sub-threshold slope and DIBL mismatch beyond 22nm. Pablo Royer, Binjie Cheng, Asen Asenov, & Marisa López-Vallejo. 18th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2013). Glasgow, Scotland. September 2013.
  3. A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node. Pablo Royer, & Marisa López-Vallejo. 23rd ACM international conference on Great lakes symposium on VLSI (GLSVLSI 2013). Paris, France. May 2013.
  4. Model Validation and Simulation Framework for Novel Nanometer Devices. Fernando García Redondo, Marisa López-Vallejo, Pablo Ituero, and Carlos López Barrio. Conference on Design of Circuits and Integrated Systems 2012 (DCIS 2012) Avignon (France) 28-30 September 2012.
  5. A CAD Framework for the Characterization and Use of Memristor Models. Fernando García, Marisa López-Vallejo, Pablo Ituero and Carlos López Barrio. IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2012 (SMACD2012) Seville, Spain. 19 - 21 September 2012.

High Performance Digital Design in Reconfigurable Architectures

  1. "Floating-Point Exponentiation Units for Reconfigurable Computing", Florent De Dinechin Pedro Echeverria Marisa Lopez-Vallejo Bogdan Pasca, ACM Transactions on Recon.gurable Technology and Systems, 2012 Accepted.
  2. High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator, Pedro Echeverría, Marisa López-Vallejo, Journal of Signal Processing Systems, Springer New York, 2012 Issn: 1939-8018, Doi: 10.1007/s11265-012-0684-4, Impact Factor 2011: 0.672.
  3. Cycle-accurate configuration layer model for Xilinx Virtex FPGAs, Herrera-Alzu, I.; Lopez-Vallejo, M.; Radiation and Its Effects on Components and Systems (RADECS), 2011 12th European Conference on , vol., no., pp.182-185, 19-23 Sept. 2011 doi: 10.1109/RADECS.2011.6131394
  4. Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs. Ignacio Herrera-AlzuMarisa López-Vallejo, INTEGRATED CIRCUIT AND SYSTEM DESIGN. POWER AND TIMING MODELING, OPTIMIZATION, AND SIMULATION (Patmos 2012) Lecture Notes in Computer Science, 2011, Volume 6951/2011, 133-142,
  5. Real Time FPGA Implementation of an Modulation Classifier for Electronic Warfare Applications, Jesús Grajal, Omar Yeste-Ojeda, Miguel A. Sánchez, Mario Garrido, y Marisa López-Vallejo IEEE 19th European Signal Processing Conference, Eusipco, pages 1514–1518, 2011 
  6. Customizing floating-point units for FPGAs: Area-performance-standard trade-offs, Pedro Echeverría, Marisa López-Vallejo, Microprocessors and Microsystems, Volume 35, Issue 6, August 2011, Pages 535-546, ISSN 0141-9331, 10.1016/j.micpro.2011.04.004. Impact Factor 2010: 0.545.
  7. Implementing FFT-based Digital Channelized Receivers on FPGA Platforms, M. A. Sánchez, M. Garrido, M. L. López Vallejo y J. Grajal, IEEE Trans. on Aeroespace and Electronic Systems.October 2008. Impact Factor 2008: 1,024. 
  8. Development of a standard single floating-point library and its encapsulation for reuse, Pedro Echeverría, Miguel Angel Sánchez, Marisa López-Vallejo, Carlos López Barrio. Design of Circuits and Integrated Systems Conference, Zaragoza (Spain), November 2009.
  9. Inversion-based FPGA Random Number Generation using Quintic Hermite Interpolation, Pedro Echeverría, Marisa López-Vallejo, Carlos López-Barrio. Design of Circuits and Integrated Systems Conference, Grenoble (France), November 2008.
  10. Designing Highly Parameterized Hardware using xHDL, Miguel Angel Sanchez, Pedro Echeverría, Francisco Mansilla and Marisa López-Vallejo. Forum on Specification & Design Languages, FDL'08. Sttugart (Germany) September 2008. 
  11. Variance Reduction Techniques for Monte Carlo Simulations. A Parameterizable FPGA Approach. Pedro Echeverría, Marisa López-Vallejo, José María Pesquero. IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, Malta. Sept. 2008.
  12. An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithmetic P. Echeverría and M. López-Vallejo. 8th Conference on Real Numbers and Computers, Santiago de Compostela (Spain), July 2008. 
  13. An FPGA run-time parameterisable Log-Normal Random Number Generator P. Echeverría, D. B. Thomas, M. López-Vallejo and W. Luk. International Workshop on Applied Reconfigurable Computing, London (United Kingdom), March 2008
  14. FPGA Gaussian Random Number Generator based on quintic Hermite interpolation inversion Pedro Echeverría and Marisa López-Vallejo. IEEE International Midwest Symposium on Circuits and Systems, Montreal (Canada), August 2007.
  15. Implementation Trade-offs of the Jacobian Logarithm for Several Hardware Platforms. Pablo Ituero, Pedro Echeverría, Marisa López-Vallejo and Carlos López-Barrio. XXI Conference on Design of Circuits and Integrated Systems. Barcelona 22-24 November 2006.
  16. Design of a Pipelined Hardware Architecture for Real-Time Neural Network Computations. J. L. Ayala, A. G. Lomeña, M. López-Vallejo, A. Fernández. IEEE Midwest Symposium on Circuits and Systems, Tulsa (Oklahoma, USA), August 2002
  17. A Fast, Configurable Digital Neural Network ASIC for High-Speed Applications. J. L. Ayala, A. G. Lomeña, M. López-Vallejo, A. Fernández. Design of Circuits and Integrated Systems Conference, Oporto (Portugal), November 2001
  18. A Pipeline Frequency-Domain Reed-Solomon Decoder for Application in ATM Networks. A. G. Lomeña Moreno, J. C. López López and A. Royo Oreja. XIV Design of Circuits and Integrated Systems Conference, Palma de Mallorca, Spain, November 16-19, 1999 

Low Power Design

  1. Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs, Echeverria, P.; Lopez-Vallejo, M.; Bolognesi, W.; Lopez-Barrio, C.; , Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on , vol., no., pp.423-426, 13-16 Dec. 2009
  2. A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. José Luis Ayala, Marisa López-Vallejo, Carlos A. López Barrio and Alex Veidenvaum. International Journal of Embedded Systems 2008 - Vol. 3, No.4 pp. 285 - 293.
  3. Joint Hardware-Software Leakage Minimization Approach For The Register File of VLIW Embedded Architectures. D. Atienza, , P. Raghavan, J. L. Ayala, G. De Micheli, F. Catthoor, D. Verkerst, M. López-Vallejo. Integration, The VLSI Journal, vol 41, issue1, pp 38-48, Jan. 2008. Impact Factor (2008): 0,4
  4. Power Considerations in Banked CAMs: A leakage Reduction Approach P. Echeverría, José L. Ayala and M. López-Vallejo. Hindawi Journal on VLSI Design, vol 8, Issue 2, January 2008.
  5. Energy-aware compilation and hardware design for VLIW embedded systems. J.L. Ayala, M. López-Vallejo, D. Atienza, P. Raghavan, F. Catthoor and D. Verkest. Inderscience 
  6. Int. J. Embedded Systems. Vol.3 Num 1/2 Dec. 2007.
  7. Exploring Performance-Power Trade-offs forLook-Up Tables in SRAM-based FPGAs, Pedro Echeverría, Marisa López-Vallejo, Walter Bolognesi, Carlos López-Barrio. IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, Tunisia December 2009
  8. Experimental Methodology for Power Characterization of FPGAs Ignacio Herrera-Alzu, Miguel-Angel Sánchez-Marcos, Marisa López-Vallejo and Pedro Echeverría. IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, Malta. Sept. 2008.
  9. Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors, Raghavan, P.; Ayala, J.L.; Atienza, D.; Catthoor, F.; De Micheli, G.; Lopez-Vallejo, M., Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on , vol., no., pp.121-124, 27-30 May 2007.
  10. Leakage Energy Reduction in Banked Content Addressable Memories. Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. IEEE International Conference on Electronics, Circuits and Systems, Nice (France), December 2006.
  11. Automated design space exploration of FPGA-based FFT architectures based on area and power estimation, Sanchez, M.A.; Garrido, M.; Vallejo, M.L.; Lopez-Barrio, C.; IEEE International Conference on Field Programmable Technology, 2006. FPT 2006. Dec. 2006 Page(s):127 - 134.
  12. Energy-Aware Compilation and Hardware Design for VLIW Embedded Systems. José L. Ayala, David Atienza, Praveen Raghavan, Marisa López-Vallejo, Francky Catthoor, Diederik Verkest. International Journal of Embedded Systems, vol. 3, issue 1-2, pp. 73-82, 2007.
  13. Compiler-driven Leakage Energy Reduction in Banked Register Files David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo. IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, Montpellier (France), September 2006.
  14. A Banked Precomputation-Based CAM Architecture for Low-Power Storage-Demanding Applications Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. IEEE Mediterranean Electrotechnical Conference, Malaga (Spain), May 2006.
  15. A Low-Power Pipelined CAM for High-Performance IP Routing Pedro Echeverría, José L. Ayala, Marisa López-Vallejo. IEEE International Caribbean Conference on Devices, Circuits and Systems, Playa del Carmen (Mexico), April 2006.
  16. Energy-Aware Compilation and Delay Impact Minimization for VLIW Embedded Systems José L. Ayala, David Atienza, Praveen Raghavan, Marisa López-Vallejo, Francky Catthoor. IEEE Workshop on Innovative Architectures, Hawaii, January 2006.
  17. Practical Implementation of Low-Power Content Addressable Memories P. Echeverría, J. L. Ayala, M. López-Vallejo. Design of Circuits and Integrated Systems Conference, Lisboa (Portugal), November 2005.
  18. Digital channelised receivers on FPGAs platforms Miguel Ángel Sanchez, Mario Garrido, Marisa Lóopez-Vallejo, Jesús Grajal and Carlos Lopez-Barrio. 2005 IEEE International Radar Conference. 9-12 May 2005 Page(s):816 - 821. 
  19. Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs J. L. Ayala, D. Atienza, M. López-Vallejo, J. M. Mendías, R. Hermida, C. A. López. IEEE Workshop on Innovative Architectures, Hawaii, January 2005.
  20. Reducing the Energy Consumption of the Register File for In-Order Architectures J. L. Ayala, M. López-Vallejo, Alex Veidenbaum, Carlos A. López. To be published in International Journal of Embedded Systems , February 2005.
  21. Integrating Functional and Power Simulation in Embedded Systems Design J. L. Ayala, M. López-Vallejo. Journal of Embedded Computing, Fall 2006.
  22. Power Characterization of RAMs. An Experimental Approach F. Rellán, J. L. Ayala, M. López-Vallejo. Design of Circuits and Integrated Systems Conference, Bordeaux (France), November 2004.
  23. Improving Register File Banking with a Power-Aware Unroller J. L. Ayala, M. López-Vallejo. Workshop on Power-Aware Real-Time Computing (in conjunction with ACM International Conference on Embedded Software), Pisa (Italy), September 2004.
  24. A Compiler-assisted Banked Register File Architecture J. L. Ayala, M. López-Vallejo, A. Veidenbaum. Workshop on Application Specific Processors (in conjunction with IEEE International Conference on Hardware/Software Codesign and System Synthesis), Stockholm (Sweden), September 2004.
  25. Power Estimation and Power Optimization Policies for Processor-Based Systems. J. L. Ayala, M. López-Vallejo. SIGDA Ph.D. Forum at Design Automation Conference, San Diego (California, USA), June 2004. (see also the poster)
  26. Power-aware Register Renaming in High-Performance Processors using Compiler Support. J. L. Ayala, M. López-Vallejo, A. Veidenbaum. IEEE Workshop on Innovative Architectures, Hawaii, January 2004.
  27. Energy-Efficient Register Renaming in High-Performance Processors. J. L. Ayala, M. López-Vallejo, A. Veidenbaum. Workshop on Application Specific Processors (in conjunction with IEEE International Symposium on Microarchitecture), San Diego (California, USA), December 2003.
  28. Power-Aware Compilation for Register File Energy Reduction. J. L. Ayala, A. Veidenbaum, M. López-Vallejo. International Journal of Parallel Programming (Kluwer Academic Publishers), Vol. 31, No. 6, pp. 449-465, December 2003. Impact Factor 2006: 0,289 
  29. A Case Study on Power Dissipation in the Memory Hierarchy of Embedded Systems. J. L. Ayala, M. López-Vallejo and C.A. López Barrio. Design of Circuits and Integrated Systems Conference, Ciudad Real (Spain), November 2003
  30. A Unified Framework for Power-Aware Design of Embedded Systems. J. L. Ayala, M. López-Vallejo. IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, Torino (Italy), September 2003. Also published as Lecture Notes on Computer Science, vol. 2799 (Springer Verlag)
  31. Energy Aware Register File Implementation through Instruction Predecode.. J. L. Ayala, M. López-Vallejo, A. Veidenbaum, C. A. López. IEEE International Conference on Application-Specific Systems, Architectures and Processors, The Hague (Netherlands), June 2003
  32. Reducing Register File Energy Consumption using Compiler Support.. J. L. Ayala, A. Veidenbaum. Workshop on Application Specific Processors (in conjunction with IEEE International Symposium on Microarchitecture), Istanbul (Turkey), November 2002. Best Student Paper Award
  33. A Low-Power Architecture for Maximum a Posteriori Decoding. M.L. López-Vallejo, S. A. Mujtaba and I. Lee. IEEE Asilomar Conference 2002, California, USA. November 2002.
  34. Data-Quantization Policies for Power and Area Minimization of Hardware Neural Networks. J. L. Ayala, M. López-Vallejo. Design of Circuits and Integrated Systems Conference, Santander (Spain), November 2002
  35. Block Processing Technique for Low Power Turbo Decoder Design. I. Lee, M.L. López Vallejo y S. A. Mujtaba. Vehicular Technology Conference 2002, Birmingham, Al, USA. Mayo 2002 

Application Specific Architectures

  1. Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio Pablo Ituero, and Marisa López-Vallejo, ETRI Journal, vol.30, no.1, Feb. 2008, pp.113-128. Impact Factor 2008: 1,109 
  2. Joint Source-Channel Decoding ASIP Architecture for Sensor Networks Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, and Jon Altuna. Lecture Notes on Computer Science, vol. 4523, pp. 221–231, 2007. Springer-Verlag Berlin Heidelberg 2007 
  3. New Schemes in Clustered VLIW Processors Applied to Turbo Decoding.P. Ituero, M. López-Vallejo. 17th IEEE International Conference on Application-Specific Systems, Architecture Processors, Steamboat Springs, Colorado, September 11-13, 2006
  4. A Configurable Application Specific Processor for Turbo Decoding. P. Ituero, M. Lopez-Vallejo, S.A. Mujtaba. Conference Record of the Thirty-Ninth Asilomar Conference on Signals, Systems and Computers. October 28 - November 1, 2005 Page(s):1356 - 1360

Reconfigurable and Embedded Systems Design Automation

  1. Hardware Reuse Improvement through the Domain Specific Language dHDL. Miguel-Angel Sanchez-Marcos, Marisa Lopez-Vallejo and Carlos A. Iglesias. 10th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA-12), Madrid, July 2012.
  2. Improving Hardware Reuse through XML-based Interface Encapsulation, Miguel-Angel Sanchez-Marcos, Marisa Lopez-Vallejo, Carlos A. Iglesias and Carlos A. Lopez-Barrio. 17th IEEE International Conference on Engineering of Complex Computer Systems, Paris, July 2012.
  3. Designing highly parameterized hardware using xHDL, Sanchez, M.A.; Echeverria, P.; Mansilla, F.; Lopez-Vallejo, M.; Specification, Verification and Design Languages, 2008. FDL 2008. Forum on , vol., no., pp.78-83, 23-25 Sept. 2008
  4. On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques. M. López-Vallejo and J. C. López. ACM Trans. on Design Automation of Electronic Systems, July 2003, Vol. 8 Issue 3. Impact Factor 2009: 1.099. 
  5. State Space Compression in History Driven Quasi-Static Scheduling A. G. Lomeña Moreno, M. L. López Vallejo, Y. Watanabe and A. Kondratyev. in Embedded Software for SOC. Kluwer Academic Publishers (currently in press, to be published on June 2003)
  6. An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. A. G. Lomeña Moreno, M. L. López Vallejo, Y. Watanabe and A. Kondratyev. Design Automation and Test in Europe Conference, Munich, Germany, 3-7 March 2003
  7. Aplicacion de metodologias de co-diseno hw/sw de sistemas empotrados para el diseno e implementacion de un control de accesos distribuido. J. L. Ayala, A. G. Lomena, M. Lopez-Vallejo. Telecommunication Electronics and Control, Santiago de Cuba (Cuba), July 2002 (in Spanish).
  8. Hardware-Software Co-design of a Cryptographic Application. D. Matilla, M. López-Vallejo, A. Royo. Design of Circuits and Integrated Systems Conference, Oporto (Portugal), November 2001, pp 100-105.
  9. Applying Data Mining Techniques to Tune System Scheduling A. G. Lomeña Moreno, M. L. López Vallejo and A. García Quintas. XVI Design of Circuits and Integrated Systems Conference, Oporto, Portugal, November 20-23, 2001
  10. Multi-way Clustering Techniques for System Level Partitioning. M. López-Vallejo, and J.C. López. 14th IEEE ASIC/SOC Conference, Washington DC, September 2001, pp. 242-247
  11. Constraint-driven System Level Partitioning. M. López-Vallejo, J. Grajal and J.C. López. IEEE DATE Conference, Paris, March 2000, pp. 411-416.
  12. A Reed-Solomon Encoder/Decoder ASIC for Application in ATM Networks. A. G. Lomeña Moreno, J. C. López López and A. Royo Oreja. User Forum Design Automation and Test in Europe Conference, Paris, France, March 27-30, 2000 (Abstract), (Poster)
  13. Hardware-Software Partitioning at the Knowledge Level. M.L. López Vallejo, J.C. López and C.A. Iglesias. Journal of Applied Intelligence, March 1999, pp. 173-184.

Education on Electronics

  1. Providing Self-learning to Students of Highly Attended Electronics Courses through the Remote Access to a Microelectronics Laboratory. Marisa López-Vallejo, Ángel Fernández, Pablo Ituero y Gabriel Caffarena, IEEE EAEEIE Annual Conference. Valencia  22-24 June 2009
  2. Acceso Remoto al Laboratorio de Diseño Microelectrónico como Complemento a las Asignaturas Teóricas Relacionadas. Marisa López-Vallejo, Ángel Fernández, Pablo Ituero y Gabriel Caffarena.  II Jornadas Internacionales U.P.M sobre Innovación Educativa y Convergencia Europea (INECE'08). Madrid, Spain 9-11 December 2008.